It is well known that integrated circuits, for example, microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), etc. are often capable of operation in both mission and test modes. In mission mode, mission circuitry in the integrated circuit performs mission functions that the integrated circuit is intended to perform when deployed in the field. In a test mode, test circuitry in the integrated circuit performs test functions, for example, testing the physical integrity and/or functional performance of the mission circuitry. Such test functions can be performed during the integrated circuit manufacturing process, such as wafer probe testing of integrated circuits at the wafer level, or testing of the final packaged die. Test functions can also be performed after deployment of the integrated circuit, such as built-in-system-test (BIST). Integrated circuits are also commonly provided with boundary scan test functionality that permits controlling and/or capturing inputs and outputs of the mission circuitry for test purposes. The types of mission mode and test mode operations described above are well known in the art.
FIG. 1 diagrammatically illustrates a conventional integrated circuit apparatus having mission functionality and test functionality. The integrated circuit apparatus of FIG. 1 includes a boundary scan register (BSR) 15 for scanning test signals between externally accessible boundary scan input (BSI) and boundary scan output (BSO) terminals of the integrated circuit apparatus. As is well known in the art, the BSR 15 permits test signals (used in a test mode of operation) to be scanned into the integrated circuit apparatus from an external test apparatus, and/or to be captured from the integrated circuit apparatus and then scanned out to an external test apparatus. As shown in FIG. 1, mission signals (designated generally at 14) produced by mission circuitry 11 can be captured into BSR 15 and then scanned out via the BSO terminal. The mission signals 14 are also input to respective ones of a plurality of switching circuits designated collectively at 17. Boundary scan test signals (designated generally at 12) from the BSR 15 are also input to respective ones of the switching circuits 17. Furthermore, test signals (designated generally at 16) produced by test circuitry 13 are input to respective ones of the switching circuits 17. The test circuitry 13 provides the test signals 16 as a result of a testing operation (e.g., manufacturing test, BIST, etc.) that the test circuitry 13 applies to the mission circuitry independently of terminal BSI, terminal BSO, and BSR 15. The switching circuits 17 provide respective output signals (designated collectively at 18) to respective ones of a plurality of output circuits designated collectively at 19.
Each of the of the output circuits 19 drives a corresponding output signal of the integrated circuit apparatus from an output terminal (not explicitly shown) of the integrated circuit apparatus to a destination that is external to the integrated circuit apparatus. Any one or more of the signals at 18, as output from the switching circuits at 17, can be either the actual integrated circuit output signal intended for an external destination, or a control signal that controls the associated output circuit at 19 for driving the actual integrated circuit output signal (shown by broken line at 10) to the external destination. Examples of control signals at 18 include an output enable signal, and an input/output control signal (such as associated with a bidirectional terminal).
FIG. 2 diagrammatically illustrates one of the switching circuits shown at 17 in FIG. 1, designated as 17A in FIG. 2. The switching circuit 17A outputs a corresponding one of the signals shown at 18 in FIG. 1, designated as 18A in FIG. 2. This switching circuit output signal 18A is input to a corresponding one of the output circuits shown at 19 in FIG. 1, designated as 19A in FIG. 2. FIG. 2 also illustrates the aforementioned situation where the signal 18A is a an output control signal that controls the driving of the actual signal (i.e., one of the signals shown at 10 in FIG. 1, designated as 10A in FIG. 2) that is to be output to an external destination.
The switching circuit 17A includes first and second selectors 21 and 23 that are respectively controlled by external control signals TM and MODE provided via externally accessible input terminals of the integrated circuit apparatus. One input of the selector 21 receives one of the test signals 16 (designated as test signal 16A in FIG. 2) from the test circuitry 13 of FIG. 1. The other input of selector 21 receives one of the mission signals 14 (designated as mission signal 14A in FIG. 2) from the mission circuitry 13 of FIG. 1. The output 22 of the selector 21 is coupled to one input of the selector 23. The other input of the selector 23 receives one of the boundary scan test signals 12 (designated as boundary scan test signal 12A in FIG. 2) from the BSR 15 of FIG. 1. Under appropriate control of TM and MODE, the switching circuit 17A routes a selected one of the signals 12A, 14A and 16A to the output circuit 19A. Thus, the switching circuit 17A provides signal paths that permit the BSR 15, mission circuitry 11, and test circuitry 13 to share the output circuit 19A. Each of the switching circuits at 17 in FIG. 1 is the same as the switching circuit 17A of FIG. 2, and routes a corresponding set of mission (see 14), test (see 16) and boundary scan test (see 12) signals to a corresponding output circuit (see 19).
It can be seen from the foregoing that the above-described prior art approach for providing test mode capabilities in an integrated circuit apparatus incurs a time delay cost. More specifically, each mission signal (e.g., mission signal 14A of FIG. 2) must traverse a switching delay imposed by the associated switching circuit 17 (e.g., switching circuit 17A of FIG. 2).
It is therefore desirable to provide test mode capabilities in an integrated circuit apparatus without the associated time delay cost incurred in the above-described prior art approach.